Design & specifications¶
If you want to know how BeagleV-Fire board is designed and what are it’s high-level specifications then this chapter is for you. We are going to discuss each hardware design element in detail and provide high-level device specifications in a short and crisp form as well.
Tip
For hardware design files and schematic diagram you can checkout BeagleV-Fire GitLab repository: https://git.beagleboard.org/beaglev-fire/beaglev-fire
Block diagram¶
Fig. 252 System block diagram¶
Fig. 253 Power tree diagram¶
Fig. 254 I2C tree diagram¶
System on Chip (SoC)¶
Fig. 255 SoC bank0¶
Fig. 256 SoC bank1¶
Fig. 257 SoC bank2¶
Fig. 258 SoC bank3¶
Fig. 259 SoC bank4¶
Fig. 260 SoC power¶
Power management¶
Fig. 261 DC 5V input¶
Fig. 262 Ideal diode¶
Fig. 263 VCC 1V0¶
Fig. 264 VCC 1V1¶
Fig. 265 VCC 1V8¶
Fig. 266 VCC 2V5¶
Fig. 267 VCC 3V3¶
Fig. 268 VCCA 1V0¶
Fig. 269 VIO enable¶
General Connectivity and Expansion¶
USB-C port¶
Fig. 270 USB C¶
P8 & P9 cape header pins¶
Fig. 271 P8 cape header¶
Fig. 272 P9 cape header¶
Fig. 273 Cape header voltage level translator¶
ADC¶
Fig. 274 16bit Delta-Sigma ADC¶
Fig. 275 ADC LDO power supply¶
Buttons and LEDs¶
User LEDs and Power LED¶
Fig. 276 User LEDs and power LED¶
User and reset button¶
Fig. 277 User button¶
Fig. 278 Reset button¶
Connectivity¶
Ethernet¶
Fig. 279 Gigabit ethernet¶
Memory, Media and Data storage¶
DDR memory¶
Fig. 280 LPDDR memory¶
eMMC¶
Fig. 281 EMMC flash storage¶
microSD¶
Fig. 282 SD Card socket¶
EEPROM¶
Fig. 283 EEPROM¶
SPI flash¶
Fig. 284 SPI Flash¶
Multimedia I/O¶
CSI¶
Fig. 285 CSI¶
Debug¶
UART debug port¶
Fig. 286 UART debug header¶
JTAG debug port¶
Fig. 287 JTAG debug header¶
Mechanical Specifications¶
Parameter |
Values |
|---|---|
Size |
86.38 * 54.61 * 18.8 mm |
Max heigh |
18.8 mm |
PCB Size |
86.38 * 54.6 mm |
PCB Layers |
12 Layers |
PCB Thickness |
1.6 mm |
RoHS compliant |
Yes |
Gross Weight |
106 g |
Net weight |
45.8 g |