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Design & specifications

If you want to know how BeagleV-Fire board is designed and what are it’s high-level specifications then this chapter is for you. We are going to discuss each hardware design element in detail and provide high-level device specifications in a short and crisp form as well.

Tip

For hardware design files and schematic diagram you can checkout BeagleV-Fire GitLab repository: https://git.beagleboard.org/beaglev-fire/beaglev-fire

Block diagram

System block diagram

Fig. 252 System block diagram

Power tree diagram

Fig. 253 Power tree diagram

I2C tree diagram

Fig. 254 I2C tree diagram

System on Chip (SoC)

SoC bank0

Fig. 255 SoC bank0

SoC bank1

Fig. 256 SoC bank1

SoC bank2

Fig. 257 SoC bank2

SoC bank3

Fig. 258 SoC bank3

SoC bank4

Fig. 259 SoC bank4

SoC power

Fig. 260 SoC power

Power management

DC 5V input

Fig. 261 DC 5V input

Ideal diode

Fig. 262 Ideal diode

VCC 1V0

Fig. 263 VCC 1V0

VCC 1V1

Fig. 264 VCC 1V1

VCC 1V8

Fig. 265 VCC 1V8

VCC 2V5

Fig. 266 VCC 2V5

VCC 3V3

Fig. 267 VCC 3V3

VCCA 1V0

Fig. 268 VCCA 1V0

VIO enable

Fig. 269 VIO enable

General Connectivity and Expansion

USB-C port

USB C

Fig. 270 USB C

P8 & P9 cape header pins

P8 cape header

Fig. 271 P8 cape header

P9 cape header

Fig. 272 P9 cape header

Cape header voltage level translator

Fig. 273 Cape header voltage level translator

ADC

16bit Delta-Sigma ADC

Fig. 274 16bit Delta-Sigma ADC

ADC LDO power supply

Fig. 275 ADC LDO power supply

Buttons and LEDs

User LEDs and Power LED

User LEDs and power LED

Fig. 276 User LEDs and power LED

User and reset button

User button

Fig. 277 User button

Reset button

Fig. 278 Reset button

Connectivity

Ethernet

Gigabit ethernet

Fig. 279 Gigabit ethernet

Memory, Media and Data storage

DDR memory

LPDDR memory

Fig. 280 LPDDR memory

eMMC

EMMC flash storage

Fig. 281 EMMC flash storage

microSD

SD Card socket

Fig. 282 SD Card socket

EEPROM

EEPROM

Fig. 283 EEPROM

SPI flash

SPI Flash

Fig. 284 SPI Flash

Multimedia I/O

CSI

CSI

Fig. 285 CSI

Debug

UART debug port

UART debug header

Fig. 286 UART debug header

JTAG debug port

JTAG debug header

Fig. 287 JTAG debug header

Mechanical Specifications

Table 79 Dimensions & weight

Parameter

Values

Size

86.38 * 54.61 * 18.8 mm

Max heigh

18.8 mm

PCB Size

86.38 * 54.6 mm

PCB Layers

12 Layers

PCB Thickness

1.6 mm

RoHS compliant

Yes

Gross Weight

106 g

Net weight

45.8 g